• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A signal phase difference quantizing circuit is provided to be capable of quantizing a phase difference between two signals by a simple circuit configuration. CONSTITUTION: A signal phase difference quantizing circuit comprises a NOR gate(NOR2), a buffer chain(20) and a plurality of D-flip flops(21-25). The NOR gate(NOR2) receives a first input signal(S0) and a second input signal(S1) having a predetermined phase difference with the first input signal(S0), and outputs a phase difference signal(S-diff) between the first and second input signals(S0,S1). The buffer chain(20) consists of a plurality of buffers(B1-Bn) each corresponding to the D-flip flops(21-25) and having an unit delay time. Each of the D-flip flops(21-25) has a clock terminal(CLK) connected to receives an inverted version of the phase difference signal(S-diff) and a data input terminal(D) connected to receive an output signal of a corresponding buffer. Each of the D-flip flops(21-25) stores an output signal of a corresponding buffer when the phase difference signal(S-diff) transitions from high to low, and is reset by a signal(END) indicating that a processing of a quantized signal is completed.
    公开号:KR20000044544A
    申请号:KR1019980061043
    申请日:1998-12-30
    公开日:2000-07-15
    发明作者:정진면
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    Circuit for Quantizing Phase Difference of Signal
    The present invention relates to a circuit technology for quantizing the phase difference between two signals so that the quantized phase difference can be processed by a digital circuit.
    In general, when an input signal passes through any semiconductor element, it is delayed by an arbitrary time and is changed into an arbitrary signal having a phase different from that of the input signal.
    FIG. 1 is a diagram for conceptually explaining a relationship between an input signal S0 and another signal S1 having a predetermined phase difference from the input signal S0 due to a delay element.
    In this case, when the input signal S0 is expressed as a function of time, u (t), the signal S1 delayed by the delay element may be represented by u (t-t0), where t0 is a delayed time or two. The phase difference between the signals S0 and S1.
    2 is a phase difference detection circuit of two signals according to the prior art.
    As shown in the drawing, a phase difference detection circuit of two signals according to the related art receives a negative logic gate which receives two signals S0 and S1 having a certain degree of phase difference, and outputs the phase differences S1-S0 by a negative logic. NOR1). At this time, the phase difference S1-S0 is represented by a pulse width.
    3 is another phase difference detection circuit of two signals according to the prior art.
    As shown in the drawing, the phase difference detection circuit according to the related art receives two signals S0 and S1 having a certain degree of phase difference into their respective clock stages CLK and CLK1, and responds with a logic " high " 2 D flip-flops 10 and 11 outputting the levels to the output terminals Q and Q1, and output signals from the two D flip-flops 10 and 11, and are logically multiplied. Including the AND gate AND1 output as the reset signal RESET of 10 and 11, the phase and frequency difference of the two signals S0 and S1 is detected.
    When the input signal S0 changes from a logic "low" level to a logic "high" level, the logic "high" level applied to the data input terminal D of the D flip-flop 10 becomes the D flip-flop 10. When the input signal S1 changes from a logic "low" level to a logic "high" level, the logic "high" is applied to the data input terminal D1 of the D flip-flop 11. The level is transferred to the output terminal Q1 of the D flip-flop 11. In response to the "high" level output terminal Q and Q1 signals, the AND gate AND1 outputs a "high" level reset signal RESET, whereby two D flip-flops 10 and 11 are reset. The output stages Q and Q1 change to the "low" level.
    Here, the S1-S0 signals representing the phase difference between the two signals S0 and S1 are respectively output from the respective output terminals Q and Q1 of the D flip-flop 10 and 11, which are also similar to those of FIG. 1. The phase difference appears as a pulse width, so that an additional circuit is required to digitally process the detected phase difference.
    SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for quantizing a phase difference of a signal, which can be quantized in phase difference between two signals with a simple circuit configuration without an additional circuit.
    1 is a view for conceptually explaining the relationship between the input signal and another input signal having a certain phase difference due to the delay element.
    2 is a phase difference detection circuit diagram of two signals according to the prior art.
    3 is another phase difference detection circuit diagram of two signals according to the prior art.
    4 is an exemplary circuit diagram for quantizing a phase difference of a signal according to the present invention.
    * Description of the main parts of the drawing
    NOR2: Negative Logic Gate
    B1 to Bn: buffer
    21 to 25: D flip-flop
    The present invention for achieving the above object is a circuit for quantizing the phase difference of the signal, the first input signal and the second input signal having a predetermined phase difference with the first input signal received the first and second Phase difference output means for outputting a phase difference between input signals; A plurality of delay means for delaying the phase difference between the first and second input signals output from the phase difference output means in multiple stages; And a plurality of storage means for storing a delayed signal output from each of said delay means in response to a phase difference between said first and second input signals.
    DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
    4 is a circuit diagram for quantizing a phase difference of a signal according to the present invention.
    As shown in the figure, the circuit for quantizing the phase difference of the signal according to the present invention is another second input signal (S0) and another second input signal (S0) having a certain degree of phase difference from the first input signal (S0). Unit delay time by receiving a phase difference (S-diff) between the negative logic gate (NOR2) and the first and second input signals (S0 and S1) output from the negative logic gate (NOR2) to receive the negative logic sum. The phase difference S-diff between the buffer chain 20 and the first and second input signals S0 and S1 delayed through the plurality of buffers B1 to Bn having the respective clock stages CLK0 to CLKn. And a plurality of D flip-flops 21 to 25 connected to data input terminals D0 to Dn at respective output terminals of the buffers B1 to Bn. At this time, the D flip-flops 21 to 25 are triggered at the negative edge of the phase difference S-diff so that the buffers B1 to at the time when the phase difference S-diff changes from "high" to "low" Each signal output from Bn) is stored. The D flip-flops 21 to 25 are reset by receiving a signal END indicating that the processing of the quantized signal is finished as a reset signal. In this case, the phase difference S-diff, which is an output of the negative logic gate NOR2, may be used as a reset signal of the D flip-flop.
    When the first input signal S0 is input, the circuit of the present invention buffers the first input signal S0 through the plurality of buffers B1 to Bn until the second input signal S1 is input. At this time, the output signal of each buffer is weighted and quantized. The signal output from the buffer B1 closest to the first input signal S0 is the least significant bit, and the first input signal S0. The signal output from the buffer Bn farthest from the < RTI ID = 0.0 > 1) < / RTI > Next, when another second input signal S1 having a predetermined phase difference from the first input signal S0 is input following the first input signal S0, the phase difference S-diff is set to "high". Transitioning to " low " outputs the output from each buffer through the D flip-flops 21 to 25 to the output terminals Q0 to Qn to output quantized digital values. Thereafter, the D flip-flops 21 to 25 are reset by receiving the phase difference S-diff as a reset signal.
    Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
    The present invention made as described above has the effect of quantizing the phase difference between two signals with a simple circuit configuration.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] In a circuit for quantizing the phase difference of a signal,
    Phase difference output means for receiving a first input signal and a second input signal having a predetermined phase difference from the first input signal, and outputting a phase difference between the first and second input signals;
    A plurality of delay means for delaying the phase difference between the first and second input signals output from the phase difference output means in multiple stages; And
    A plurality of storage means for storing a delayed signal output from each of said delay means in response to a phase difference between said first and second input signals
    Circuit for quantizing the phase difference of the signal comprising a.
    [2" claim-type="Currently amended] The method of claim 1, wherein the phase difference output means,
    Negative logic means for negating and logically receiving the first and second input signals
    Circuit for quantizing the phase difference of the signal comprising a.
    [3" claim-type="Currently amended] The method of claim 1 or 2, wherein the plurality of storage means, respectively,
    A D flip-flop receiving a phase difference between the first and second input signals as a clock terminal and having a data input terminal connected to an output terminal of the delay unit;
    Circuit for quantizing the phase difference of the signal comprising a.
    [4" claim-type="Currently amended] The method of claim 3, wherein the D flip-flop,
    And a signal output from the delay means at the negative edge of the phase difference.
    [5" claim-type="Currently amended] The method of claim 3, wherein the D flip-flop,
    And a reset operation is performed in response to the phase difference between the first and second input signals.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6359479B1|2002-03-19|Synchronizing data transfers between two distinct clock domains
    US5315181A|1994-05-24|Circuit for synchronous, glitch-free clock switching
    US5231636A|1993-07-27|Asynchronous glitchless digital MUX
    AU640448B2|1993-08-26|Digital clock buffer circuit providing controllable delay
    EP0477582B1|1997-06-25|Digital frequency multiplication and data serialization circuits
    US6134155A|2000-10-17|Synchronized circuit for coordinating address pointers across clock domains
    US6710726B2|2004-03-23|Serializer-deserializer circuit having increased margins for setup and hold time
    JP4072419B2|2008-04-09|Output control signal generation circuit and output control signal generation method for synchronous semiconductor memory device
    US5175819A|1992-12-29|Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer
    US6819157B2|2004-11-16|Delay compensation circuit
    US5233617A|1993-08-03|Asynchronous latch circuit and register
    US6279073B1|2001-08-21|Configurable synchronizer for double data rate synchronous dynamic random access memory
    US5909133A|1999-06-01|Clock signal modeling circuit
    US7394722B2|2008-07-01|Method for controlling data output timing of memory device and device therefor
    DE10102887B4|2006-01-05|A delay device having a delay lock loop and methods for calibrating the same
    EP1565803B1|2006-03-22|Clock synchronization circuit
    US5905766A|1999-05-18|Synchronizer, method and system for transferring data
    TWI363348B|2012-05-01|Latency counter
    US6906555B2|2005-06-14|Prevention of metastability in bistable circuits
    JP4883850B2|2012-02-22|Semiconductor device
    US6260152B1|2001-07-10|Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
    US7292500B2|2007-11-06|Reducing read data strobe latency in a memory system
    US6081145A|2000-06-27|Semiconductor integrated circuit device
    US6917230B2|2005-07-12|Low pass filters in DLL circuits
    US20110116337A1|2011-05-19|Synchronising between clock domains
    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-12-30|Application filed by 김영환, 현대전자산업 주식회사
    1998-12-30|Priority to KR1019980061043A
    2000-07-15|Publication of KR20000044544A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980061043A|KR20000044544A|1998-12-30|1998-12-30|Circuit for quantizing signal phase difference|
    [返回顶部]